View UPD78078GF-XXX-3BA_3244539.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data sheet description the m pd78076 and 78078, which are the m pd78078 subseries products of the 78k/0 series, are suitable for application in av products. besides a high-speed, high-performance cpu, these microcontrollers have internal rom, ram, i/o ports, 8-bit resolution a/d converter, 8-bit resolution d/a converter, timer, serial interface, real-time output port, interrupt control, and various other peripheral hardware. a one-time prom version and an eprom version (common name: m pd78p078), both of which can operate in the same power supply voltage range as the mask rom version, and various development too ls are also available. the details of the functions are described in the following users manuals. be sure to read them before designing. m pd78078, 78078y subseries users manual: u10641e 78k/0 series users manual C instructions: u12326e features ? internal high-capacity rom and ram item program data memory part memory internal high-speed internal buffe r internal expansion package number (rom) ram ram ram m pd78076 48 kbytes 1024 bytes 32 bytes 1024 bytes 100-pi n plasti c qfp ( 1 4 20 mm, resin thickness 2.7 m m ) 100-pin plastic qfp m pd78078 60 kbytes (1 4 14 mm, resin thickness 1.45 mm) 100-pin plastic lqfp note (1 4 14 mm, resin thickness 1.40 mm) 8-bit single-chip microcontrollers mos integr a ted circuit m pd78076, 78078 the information in this document is subject to change without notice. documen t no. u10167ej3v0ds00 (3rd edition) date published november 1997 n printed in japan 1994 the mark shows major revised points. not e under development ? external memory expansion space: 64 kbytes ? minimum instruction execution time can be changed from high-speed (0.4 m s) to ultra-low-speed (122 m s) ? i/o ports: 88 (n-ch open-drain: 8) ? 8-bit resolution a/d converter: 8 channels ? 8-bit resolution d/a converter: 2 channels ? serial interface: 3 channels ? 3-wire serial i/o/sbi/2-wire serial i/o mode: 1 channel ? 3-wire serial i/o mode: 1 channel ? 3-wire serial i/o and uart mode: 1 channel ? timer: 7 channels ? supply voltage: v dd = 1.8 to 5.5 v
2 m pd78076, 78078 applications cellular phones, cordless telephones, printers, av equipment, air conditioners, cameras, ppcs, fuzzy-logic home appliances, vending machines, etc. ordering information part number package m pd78076gf- -3ba 100-pin plastic qfp (14 20 mm, resin thickness 2.7 mm) m pd78076gc- -7ea 100-pin plastic qfp (fine pitch) (14 14 mm, resin thickness 1.45 mm) m pd78076gc- -8eu note 100-pin plastic lqfp (fine pitch) (14 14 mm, resin thickness 1.40 mm) m pd78078gf- -3ba 100-pin plastic qfp (14 20 mm, resin thickness 2.7 mm) m pd78078gc- -7ea 100-pin plastic qfp (fine pitch) (14 14 mm, resin thickness 1.45 mm) m pd78078gc- -8eu note 100-pin plastic lqfp (fine pitch) (14 14 mm, resin thickness 1.40 mm) note under development caution the m pd78076gc and m pd78078gc include two types of packages. contact an nec sales representative for an available package. remark indicates the rom code suffix.
3 m pd78076, 78078 78k/0 series development these products are a further development in the 78k/0 series. the designations appearing inside the boxes are subseries names. note under development 80-pin pd78098 m control tm fip tm driving 100-pin lcd driving iebus supported 42/44-pin 64-pin 64-pin 64-pin 80-pin 100-pin 80-pin 80-pin 100-pin 100-pin 80-pin 78k/0 series basic subseries for driving fip, display output total: 34 basic subseries for driving lcds, on-chip uart y subseries support i 2 c bus specification products under development products in mass production 80-pin 100-pin pd78054 m pd78014 m pd780001 m pd78002 m pd78002y m pd78083 m pd780208 m pd78044h m pd78044f m pd78064b m pd78064 m pd78098b m pd78064y m emi-noise reduced version of the pd78098 m emi-noise reduced version of the pd78078 timer was added to the pd78054 and external interface function was enhanced m i/o and fip c/d of the pd78044f were enhanced, display output total: 53 m emi-noise reduced version of the pd78064 m pd78058f m pd780058 m pd78070a m pd78078 m 80-pin pd780308 m sio of the pd78064 was enhanced, and rom and ram capacities were expanded m 100-pin pd78075b m 100-pin 100-pin pd780024 m 64-pin pd780034 m 64-pin 64-pin pd78014h m 64-pin pd78018f m m rom-less versions of the pd78078 m emi-noise reduced version of the pd78054 uart and d/a converter were added to the pd78014, and i/o was enhanced m m a/d converter of the pd780024 was enhanced m serial i/o of the pd78018f was enhanced m serial i/o of the pd78054 was enhanced and emi-noise reduced version m emi-noise reduced version of the pd78018f m serial i/o of the pd78078y was enhanced and only selected functions are provided m m m a/d converter and 16-bit timer were added to the pd78002 m a/d converter was added to the pd78002 m basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) pd780924 m 64-pin pd780964 m 64-pin pd780988 m 64-pin inverter control pd780228 m 100-pin on-chip inverter control circuit and uart. emi-noise reduced version a/d converter of the pd780924 was enhanced inverter control, timer, and sio of the pd780964 were enhanced. rom and ram capacities were expanded m i/o and fip c/d of the pd78044h were enhanced, display output total: 48 m n-ch open-drain input/output was added to the pd78044f, display output total: 34 m iebus controller was added to the pd78054 m 80-pin pd780973 m on-chip controller/driver for operating automobile meters meter control low-voltage (1.8 v) operation versions of the pd78014, with several rom and ram capacities are available pd78054y m pd78058fy m pd780024y m m pd780034y m pd780058y note pd780018ay m pd78070ay m pd78078y m pd78014y m pd78018fy m pd780308y m
4 m pd78076, 78078 the major functional differences among the subseries are shown below. function rom timer 8-bit 10-bit 8-bit serial v dd external subseries i/o min. name capacity 8-bit 16-bit watch wdt a/d a/d d/a interface value expansion control m pd78075b 32 k to 40 k 4 ch 1 ch 1 ch 1 ch 8 ch C 2 ch 3 ch (uart: 1 ch) 88 1.8 v ? m pd78078 48 k to 60 k m pd78070a C 61 2.7 v m pd780058 24 k to 60 k 2 ch 3 ch (time division 68 1.8 v uart: 1 ch) m pd78058f 48 k to 60 k 3 ch (uart: 1 ch) 69 2.7 v m pd78054 16 k to 60 k 2.0 v m pd780034 8 k to 32 k C8 chC 3 ch (uart: 1 ch, 51 1.8 v m pd780024 8 ch C time division 3-wire: 1 ch) m pd78014h 2 ch 53 m pd78018f 8 k to 60 k m pd78014 8 k to 32 k 2.7 v m pd780001 8 k C C 1 ch 39 C m pd78002 8 k to 16 k 1 ch C 53 ? m pd78083 C 8 ch 1 ch (uart: 1 ch) 33 1.8 v C inverter m pd780988 32 k to 60 k 3 ch note 1 C 1 ch C 8 ch C 3 ch (uart: 2 ch) 47 4.0 v ? control m pd780964 8 k to 32 k note 2 2 ch (uart: 2 ch) 2.7 v m pd780924 8 ch C fip drive m pd780208 32 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch C C 2 ch 74 2.7 v C m pd780228 48 k to 60 k 3 ch C C 1 ch 72 4.5 v m pd78044h 32 k to 48 k 2 ch 1 ch 1 ch 68 2.7 v m pd78044f 16 k to 40 k 2 ch lcd drive m pd780308 48 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch C C 3 ch (time division 57 2.0 v C uart: 1 ch) m pd78064b 32 k 2 ch (uart: 1 ch) m pd78064 16 k to 32 k iebus m pd78098b 40 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch C 2 ch 3 ch (uart: 1 ch) 69 2.7 v ? supported m pd78098 32 k to 60 k meter m pd780973 24 k to 32 k 3 ch 1 ch 1 ch 1 ch 5 ch C C 2 ch (uart: 1 ch) 56 4.5 v C control notes 1. 16-bit timer: 2 channels 10-bit timer: 1 channel 2. 10-bit timer: 1 channel
5 m pd78076, 78078 overview of function part number m pd78076 m pd78078 item internal rom 48 kbytes 60 kbytes memory high-speed ram 1024 bytes buffer ram 32 bytes expansion ram 1024 bytes memory space 64 kbytes general-purpose registers 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution on-chip minimum instruction execution time variable function when main system 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (at 5.0-mhz operation) clock selected when subsystem 122 m s (at 32.768-khz operation) clock selected instruction set ? 16-bit operation ? multiply/divide (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulate (set, reset, test, boolean operation) ? bcd adjust, etc. i/o ports total : 88 ? cmos input : 2 ? cmos i/o : 78 ? n-ch open-drain i/o : 8 a/d converter ? 8-bit resolution x 8 channels d/a converter ? 8-bit resolution x 2 channels serial interface ? 3-wire serial i/o/sbi/2-wire serial i/o mode selectable : 1 channel ? 3-wire serial i/o mode (up to 32-byte automatic data transmit/receive function is provided) : 1 channel ? 3-wire serial i/o/uart mode selectable : 1 channel timer ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 4 channels ? watch timer : 1 channel ? watchdog timer : 1 channel timer output 5 (14-bit pwm output 1, 8-bit pwm output 2) clock output ? 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, 5.0 mhz (@ 5.0-mhz operation with main system clock) ? 32.768 khz (@ 32.768-khz operation with subsystem clock) buzzer output 1.2 khz, 2.4 khz, 4.9 khz, 9.8 khz (@ 5.0-mhz operation with main system clock) vectored maskable internal: 15, external: 7 interrupt non-maskable internal: 1 sources software 1 test input internal: 1, external: 1 supply voltage v dd = 1.8 to 5.5 v package ? 100-pin plastic qfp (14 20 mm, resin thickness 2.7 mm) ? 100-pin plastic qfp (fine pitch) (14 14 mm, resin thickness 1.45 mm) ? 100-pin plastic lqfp (fine pitch) (14 14 mm, resin thickness 1.40 mm) note note under development
6 m pd78076, 78078 contents 1. pin configuration (top view) ................................................................................................ 7 2. block diagram ........................................................................................................................... 10 3. pin functions .............................................................................................................................. 1 1 3.1 port pins ............................................................................................................................... .................... 11 3.2 non-port pins ............................................................................................................................... ........... 13 3.3 pin i/o circuits and recommended connection of unused pins ................................................... 15 4. memory space ............................................................................................................................. 19 5. peripheral hardware functions ...................................................................................... 20 5.1 ports ............................................................................................................................... ........................... 20 5.2 clock generator ............................................................................................................................... ....... 21 5.3 timer/event counter ............................................................................................................................... 21 5.4 clock output control circuit ................................................................................................................. 25 5.5 buzzer output control circuit .............................................................................................................. 25 5.6 a/d converter ............................................................................................................................... ........... 26 5.7 d/a converter ............................................................................................................................... ........... 26 5.8 serial interfaces ............................................................................................................................... ....... 27 5.9 real-time output port ............................................................................................................................ 29 6. interrupt functions and test functions ..................................................................... 30 6.1 interrupt functions ............................................................................................................................... .. 30 6.2 test functions ............................................................................................................................... .......... 33 7. external device expansion functions ........................................................................... 34 8. standby function ..................................................................................................................... 34 9. reset function ........................................................................................................................... 35 10. instruction set .......................................................................................................................... 36 11. electrical specifications .................................................................................................... 38 12. characteristic curves (reference value) .................................................................. 66 13. package drawings ................................................................................................................... 71 14. recommended soldering conditions .............................................................................. 74 appendix a. development tools ........................................................................................... 75 appendix b. related documents ........................................................................................... 78
7 m pd78076, 78078 1. pin configuration (top view) 100-pin plastic qfp (14 20 mm, resin thickness 2.7 mm) m pd78076gf- -3ba, 78078gf- -3ba cautions 1. connect ic (internally connected) pin directly to v ss . 2. connect av dd pin to v dd . 3. connect av ss pin to v ss . p120/rtp0 p121/rtp1 p122/rtp2 p123/rtp3 p124/rtp4 p125/rtp5 p126/rtp6 p127/rtp7 ic x2 x1 v dd xt2 xt1/p07 reset p00/intp0/ti00 p01/intp1/ti01 p02/intp2 p03/intp3 p04/intp4 p05/intp5 p06/intp6 av dd av ref0 p10/ani0 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 av ss p130/ano0 p131/ano1 av ref1 p70/si2/rxd p71/so2/txd p72/sck2/asck v ss p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0 p26/so0/sb1 p27/sck0 p80/a0 p81/a1 p66/wait p65/wr p64/rd p63 p62 p61 p60 p57/a15 p56/a14 v ss p55/a13 p54/a12 p53/a11 p52/a10 p51/a9 p50/a8 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 p87/a7 p86/a6 p85/a5 p84/a4 p83/a3 p82/a2 p96 p95 p94 p93 p92 p91 p90 p37 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p103 p102 p101/ti6/to6 p100/ti5/to5 p67/astb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
8 m pd78076, 78078 100-pin plastic qfp (fine pitch) (14 14 mm, resin thickness 1.45 mm) m pd78076gc- -7ea, 78078gc- -7ea 100-pin plastic lqfp (fine pitch) (14 14 mm, resin thickness 1.40 mm) m pd78076gc- -8eu note , 78078gc- -8eu note note under development cautions 1. connect ic (internally connected) pin directly to v ss . 2. connect av dd pin to v dd . 3. connect av ss pin to v ss . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 26 p15/ani5 p16/ani6 p17/ani7 av ss p130/ano0 p131/ano1 av ref1 p70/si2/r x d p71/so2/t x d p72/sck2/asck p20/si1 p21/so1 p22/sck1 p23/stb p24/busy p25/si0/sb0 p26/so0/sb1 p27/sck0 p80/a0 p84/a4 p40/ad0 p41/ad1 p42/ad2 p43/ad3 p44/ad4 p45/ad5 p50/a8 p51/a9 p52/a10 p53/a11 p54/a12 p55/a13 v ss p56/a14 p57/a15 p60 p61 p62 p63 p64/rd p122/rtp2 p121/rtp1 p120/rtp0 p36/buz p35/pcl p34/ti2 p33/ti1 p32/to2 p31/to1 p30/to0 p67/astb p66/wait p65/wr p13/ani3 p12/ani2 p11/ani1 p10/ani0 av ref0 av dd xt1/p07 xt2 v dd x1 x2 ic p06/intp6 p05/intp5 p04/intp4 p03/intp3 p02/intp2 p124/rtp4 p123/rtp3 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p14/ani4 v ss p81/a1 p82/a2 p83/a3 p47/ad7 p46/ad6 p87/a7 p86/a6 p85/a5 p100/ti5/to5 p101/ti6/to6 p37 p90 p91 p92 p93 p94 p95 p96 p103 p102 p01/intp1/ti01 p00/intp0/ti00 reset p127/rtp7 p126/rtp6 p125/rtp5
9 m pd78076, 78078 p100 to p103 : port10 p120 to p127 : port12 p130, p131 : port13 pcl : programmable clock rd : read strobe reset : reset rtp0 to rtp7 : real-time output port rxd : receive data sb0, sb1 : serial bus sck0 to sck2 : serial clock si0 to si2 : serial input so0 to so2 : serial output stb : strobe ti00, ti01 : timer input ti1, ti2, ti5, ti6 : timer input to0 to to2, to5, to6 : timer output txd : transmit data v dd : power supply v ss : ground wait : wait wr : write strobe x1, x2 : crystal (main system clock) xt1, xt2 : crystal (subsystem clock) a0 to a15 : address bus ad0 to ad7 : address/data bus ani0 to ani7 : analog input ano0, ano1 : analog output asck : asynchronous serial clock astb : address strobe av dd : analog power supply av ref0 , av ref1 : analog reference voltage av ss : analog ground busy : busy buz : buzzer clock ic : internally connected intp0 to intp6 : interrupt from peripherals p00 to p07 : port0 p10 to p17 : port1 p20 to p27 : port2 p30 to p37 : port3 p40 to p47 : port4 p50 to p57 : port5 p60 to p67 : port6 p70 to p72 : port7 p80 to p87 : port8 p90 to p96 : port9
10 m pd78076, 78078 2. block diagram remark the internal rom capacity depends on the product. rtp0/p120 to rtp7/p127 a8/p50 to a15/p57 rd/p64 wr/p65 wait/p66 astb/p67 port 0 external access ram 16-bit timer/ event counter 8-bit timer/ event counter 1 8-bit timer/ event counter 2 watchdog timer watch timer to0/p30 clock output control system control 78k/0 cpu core a/d converter interrupt control serial interface 1 serial interface 2 real-time output port d/a converter port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 12 port 13 serial interface 0 8-bit timer/ event counter 5 8-bit timer/ event counter 6 ti00/intp0/p00 ti01/intp1/p01 to1/p31 ti1/p33 to2/p32 ti2/p34 ti5/to5/p100 ti6/to6/p101 si0/sb0/p25 so0/sb1/p26 sck0/p27 si1/p20 so1/p21 sck1/p22 stb/p23 busy/p24 si2/r x d/p70 so2/t x d/p71 sck2/asck/p72 ani0/p10 to ani7/p17 av dd av ss av ref0 ano0/p130, ano1/p131 av ss av ref1 intp0/p00 to intp6/p06 buz/p36 pcl/p35 buzzer output port 8 port 9 port 10 p01 to p06 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p72 p80 to p87 p90 to p96 p100 to p103 p120 to p127 p130, p131 ad0/p40 to ad7/p47 a0/p80 to a7/p87 reset x1 x2 xt1/p07 xt2 rom v dd v ss ic p00 p07
11 m pd78076, 78078 function pin name i/o port 0 8-bit input/output port input only input input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software. input/ output input only port 1 8-bit input/output port input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software. note 2 input/ output input/ output port 2 8-bit input/output port input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software. port 3 8-bit input/output port input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software. input/ output input/ output port 4 8-bit input/output port input/output can be specified in 8-bit units. when used as an input port, an on-chip pull-up resistor can be used by means of software. test input flag (krif) is set to 1 by falling edge detection. p00 p01 p02 p03 p04 p05 p06 p07 note 1 p10 to p17 p20 p21 p22 p23 p24 p25 p26 p27 p30 p31 p32 p33 p34 p35 p36 p37 p40 to p47 input notes 1. when using the p07/xt1 pins as an input port, set to 1 bit 6 (frc) of the processor clock control register (pcc). (do not use the on-chip feedback resistor of the subsystem clock oscillator.) 2. when using the p10/ani0 to p17/ani7 pins as the a/d converter analog input, set port 1 to the input mode. at this time, on-chip pull-up resistor is automatically disconnected. 3. pin functions 3.1 port pins (1/2) si1 so1 sck1 stb busy si0/sb0 so0/sb1 sck0 to0 to1 to2 ti1 ti2 pcl buz ad0 to after reset input input input input input input ad7 input alternate function intp0/ti00 intp1/ti01 intp2 intp3 intp4 intp5 intp6 xt1 ani0 to ani7
12 m pd78076, 78078 rd wr wait astb 3.1 port pins (2/2) function pin name i/o input/ output port 5 8-bit input/output port leds can be driven directly. input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software. p50 to p57 p60 p61 p62 p63 p64 p65 p66 p67 p70 input/ output port 6 8-bit input/ output port input/output can be specified bit-wise. port 7 3-bit input/output port input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software. input/ output n-ch open-drain input/output port. an on-chip pull-up resistor can be specified by mask option. leds can be driven directly. when used as an input port, an on-chip pull-up resistor can be used by means of software. port 8 8-bit input/output port input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software. input/ output after reset input a8 to a15 alternate function input input input input port 9 7-bit input/output port input/output can be specified bit-wise. input/ output n-ch open-drain input/output port. an on-chip pull-up resistor can be specified by mask option. leds can be driven directly. when used as an input port, an on-chip pull-up resistor can be used by means of software. input input p90 p91 p92 p93 p94 p95 p96 p100 p101 p102, p103 input/ output port 10 4-bit input/output port input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software. port 12 8-bit input/output port input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software. input/ output input/ output port 13 2-bit input/output port input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software. ti5/to5 ti6/to6 input input si2/rxd so2/txd sck2/asck p71 p72 a0 to a7 p80 to p87 p120 to p127 p130, p131 rtp0 to rtp7 ano0, ano1
13 m pd78076, 78078 3.2 non-port pins (1/2) pin name i/o function after alternate reset function intp0 input external interrupt request input for which the active edge (rising edge, input p00/ti00 intp1 falling edge, or both rising and falling edges) can be specified. p01/ti01 intp2 p02 intp3 p03 intp4 p04 intp5 p05 intp6 p06 si0 input serial interface serial data input input p25/sb0 si1 p20 si2 p70/rxd so0 output serial interface serial data output input p26/sb1 so1 p21 so2 p71/txd sb0 input/ serial interface serial data input/output input p25/si0 sb1 output p26/so0 sck0 input/ serial interface serial clock input/output input p27 sck1 output p22 sck2 p72/asck stb output serial interface automatic transmit/receive strobe output input p23 busy input serial interface automatic transmit/receive busy input input p24 rxd input asynchronous serial interface serial data input input p70/si2 txd output asynchronous serial interface serial data output input p71/so2 asck input asynchronous serial interface serial clock input input p72/sck2 ti00 input external count clock input to 16-bit timer (tm0) input p00/intp0 ti01 capture trigger signal input to capture register (cr00) p01/intp1 ti1 external count clock input to 8-bit timer (tm1) p33 ti2 external count clock input to 8-bit timer (tm2) p34 ti5 external count clock input to 8-bit timer (tm5) p100/to5 ti6 external count clock input to 8-bit timer (tm6) p101/to6 to0 output 16-bit timer (tm0) output (also used for 14-bit pwm output) input p30 to1 8-bit timer (tm1) output p31 to2 8-bit timer (tm2) output p32 to5 8-bit timer (tm5) output (also used for 8-bit pwm output) p100/ti5 to6 8-bit timer (tm6) output (also used for 8-bit pwm output) p101/ti6 pcl output clock output (for main system clock, subsystem clock trimming) input p35 buz output buzzer output input p36 rtp0 to rtp7 output real-time output port from which data is output in synchronization with a trigger input p120 to p127
14 m pd78076, 78078 3.2 non-port pins (1/2) pin name i/o function after alternate reset function ad0 to ad7 input/ low-order address/data bus at external memory expansion input p40 to p47 output a0 to a7 output low-order address bus at external memory expansion input p80 to p87 a8 to a15 output high-order address bus at external memory expansion input p50 to p57 rd output external memory read operation strobe signal output input p64 wr external memory write operation strobe signal output p65 wait input wait insertion at external memory access input p66 astb output strobe output which externally latches the address information input p67 to ports 4, 5, and 8 to access external memory ani0 to ani7 input a/d converter analog input input p10 to p17 ano0, ano1 output d/a converter analog output input p130, p131 av ref0 input a/d converter reference voltage input av ref1 input d/a converter reference voltage input av dd a/d converter analog power supply. connect to v dd . av ss a/d converter and d/a converter ground potential. connect to v ss . reset input system reset input x1 input crystal resonator connection for main system clock oscillation x2 xt1 input crystal resonator connection for subsystem clock oscillation input p07 xt2 v dd positive power supply v ss ground potential ic internally connected. connect directly to v ss .
15 m pd78076, 78078 3.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 3-1. for the input/output circuit configuration of each type, see figure 3-1. table 3-1. types of pin input/output circuits (1/2) p00/intp0/ti00 2 input connect to v ss . p01/intp1/ti01 8-a input/output independently connect to v ss via a resistor. p02/intp2 p03/intp3 p04/intp4 p05/intp5 p06/intp6 p07/xt1 16 input connected to v dd . p10/ani0 to p17/ani7 11 input/output independently connect to v dd or v ss via a resistor. p20/si1 8-a p21/so1 5-a p22/sck1 8-a p23/stb 5-a p24/busy 8-a p25/si0/sb0 10-a p26/so0/sb1 p27/sck0 p30/to0 5-a p31/to1 p32/to2 p33/ti1 8-a p34/ti2 p35/pcl 5-a p36/buz p37 p40/ad0 to p47/ad7 5-e input/output independently connect to v dd via a resistor. p50/a8 to p57/a15 5-a input/output independently connect to v dd or v ss via a resistor. p60 to p63 13-b input/output independently connect to v dd via a resistor. p64/rd 5-a input/output independently connect to v dd or v ss via a resistor. p65/wr p66/wait p67/astb input/output circuit type pin name i/o recommended connection for unused pins
16 m pd78076, 78078 table 3-1. types of pin input/output circuits (2/2) input/output circuit type pin name i/o recommended connection for unused pins p70/si2/rxd 8-a input/output independently connect to v dd or v ss via a resistor. p71/so2/txd 5-a p72/sck2/asck 8-a p80/a0 to p87/a7 5-a p90 to p93 13-b input/output independently connect to v dd via a resistor. p94 to p96 5-a input/output independently connect to v dd or v ss via a resistor. p100/ti5/to5 8-a p101/ti6/to6 p102, p103 5-a p120/rtp0 to p127/rtp7 p130/ano0, 12-a input/output independently connect to v ss via a resistor. p131/ano1 reset 2 input xt2 16 leave open. av ref0 connect to v ss . av ref1 connect to v dd . av dd av ss connect to v ss . ic connect directly to v ss .
17 m pd78076, 78078 figure 3-1. pin input/output circuits (1/2) type 2 in type 8-a pullup enable data output disable v p-ch n-ch p-ch in/out dd v dd type 10-a type 11 pullup enable data output disable v p-ch n-ch p-ch in/out dd v dd type 5-a input enable type 5-e pullup enable data output disable v p-ch n-ch p-ch in/out dd v dd schmitt-triggered input with hysteresis characteristic pullup enable data open drain output disable n-ch p-ch v dd v dd p-ch in/out pullup enable data output disable input enable n-ch v dd p-ch in/out v dd p-ch p-ch n-ch v ref (threshold voltage) comparator +
18 m pd78076, 78078 figure 3-1. pin input/output circuits (2/2) type 12-a type 16 pullup enable data output disable v p-ch n-ch p-ch in/out dd v dd n-ch input enable type 13-b data output disable n-ch in/out v dd v dd rd mask option middle-voltage input buffer p-ch analog output voltage xt1 xt2 p-ch feedback cut-off p-ch
19 m pd78076, 78078 4. memory space the memory map of the m pd78076 and 78078 is shown in figure 4-1. figure 4-1. memory map notes 1. if external device expansion functions are to be employed for the m pd78078, set the size of the internal rom to 56 kbytes or below using the memory size switching register (ims). 2. the internal rom capacity depends on the product. (see the following table.) part number internal rom last address nnnnh m pd78076 bfffh m pd78078 efffh ffffh ff00h feffh fb00h faffh fee0h fedfh fae0h fadfh fac0h fabfh f800h f7ffh f400h f3ffh nnnnh+1 nnnnh 0000h nnnnh 1000h 0fffh 0800h 07ffh 0080h 007fh 0040h 003fh 0000h use prohibited use prohibited external memory program area callf entry area program area callt table area vector table area special function registers (sfr) 256 8 bits general-purpose registers 32 8 bits internal high-speed ram 1024 8 bits internal rom note 2 internal buffer ram 32 8 bits f3ffh f000h internal expansion ram 1024 8 bits use prohibited note 1 program memory space data memory space
20 m m pd78076, 78078 5. peripheral hardware functions 5.1 ports input/output ports are classified into three types. ? cmos input (p00, p07) : 2 ? cmos input/output (p01 to p06, port 1 to 5, p64 to p67, port 7, port 8, p94 to p96, port 10, port 12, port 13) : 78 ? n-ch open-drain input/output (p60 to p63, p90 to p93) : 8 total :88 table 5-1. functions of ports port name pin name function port 0 p00, p07 input only. p01 to p06 input/output port. input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software. port 1 p10 to p17 input/output port. input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software. port 2 p20 to p27 input/output port. input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software. port 3 p30 to p37 input/output port. input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software. port 4 p40 to p47 input/output port. input/output can be specified in 8-bit units. when used as an input port, an on-chip pull-up resistor can be used by means of software. the test input flag (krif) is set to 1 by falling edge detection. port 5 p50 to p57 input/output port. input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software. leds can be driven directly. port 6 p60 to p63 n-ch open-drain input/output port. input/output can be specified bit-wise. an on-chip pull-up resistor can be used by mask option . leds can be driven directly. p64 to p67 input/output port. input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software. port 7 p70 to p72 input/output port. input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software. port 8 p80 to p87 input/output port. input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software. port 9 p90 to p93 n-ch open-drain input/output port. input/output can be specified bit-wise. an on-chip pull-up resistor can be used by mask option. leds can be driven directly. p94 to p96 input/output port. input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software. port 10 p100 to p103 input/output port. input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software. port 12 p120 to p127 input/output port. input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software. port 13 p130, p131 input/output port. input/output can be specified bit-wise. when used as an input port, an on-chip pull-up resistor can be used by means of software.
21 m pd78076, 78078 5.2 clock generator there are two kinds of clock generators: main system and subsystem clock generators. it is possible to change the minimum instruction execution time. ? 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (at main system clock frequency of 5.0 mhz) ? 122 m s (at subsystem clock frequency of 32.768 khz) figure 5-1. clock generator block diagram 5.3 timer/event counter there are the following seven timer/event counter channels: ? 16-bit timer/event counter : 1 channel ? 8-bit timer/event counter : 4 channels ? watch timer : 1 channel ? watchdog timer : 1 channel table 5-2. operations of timer/event counters 16-bit timer/event 8-bit timer/event 8-bit timer/event watch timer watchdog timer counter counters 1, 2 counters 5, 6 interval timer 1 channel 2 channels 2 channels 1 channel 1 channel external event counter 1 channel 2 channels 2 channels timer output 1 output 2 outputs 2 outputs pwm output 1 output 2 outputs pulse width measurement 2 inputs square wave output 1 output 2 outputs 2 outputs one-shot pulse output 1 output interrupt request 2 2 2 1 1 test input 1 input operation mode function xt1/p07 xt2 x1 x2 stop f xt f xx watch timer, clock output function clock to peripheral hardware cpu clock (f cpu ) to intp0 sampling clock 2 f xx 2 f xx 2 f xx 2 3 f x f x 2 subsystem clock oscillator main system clock oscillator division circuit prescaler standby control circuit wait control circuit prescaler selector selector f xt 2 f xx 4 2 2 1
22 m m pd78076, 78078 figure 5-3. 8-bit timer/event counters 1, 2 block diagram figure 5-2. 16-bit timer/event counter block diagram match match clear selector 16-bit capture/ compare register (cr00) internal bus output control circuit intp1 inttm00 to0/p30 inttm01 intp0 ti01/p01/ intp1 watch timer output 2f xx f xx f xx /2 f xx /2 ti00/p00/ intp0 selector edge detector selector internal bus 16-bit capture/ compare register (cr01) pwm pulse output control circuit 16-bit timer register (tm0) 2 clear clear 11 /2 f /2 xx f xx 9 ti2/p34 ti1/p33 inttm2 to2/p32 to1/p31 match match inttm1 f /2 to xx 11 f/2 x x f /2 xx 9 f /2 to xx internal bus selector selector selector 8-bit timer register 1 (tm1) 8-bit compare register (cr20) 8-bit compare register (cr10) output control circuit 8-bit timer register 2 (tm2) output control circuit internal bus selector selector
23 m pd78076, 78078 figure 5-4. 8-bit timer/event counters 5, 6 block diagram n = 5, 6 internal bus 8-bit compare register (crn0) 8-bit timer register n (tmn) internal bus output control circuit selector 2f xx to f xx /2 9 f xx /2 11 ti5/p100/to5, ti6/p101/to6 clear ovf inttmn to5/p100/ti5, to6/p101/ti6 match
24 m pd78076, 78078 figure 5-5. watch timer block diagram figure 5-6. watchdog timer block diagram f w 4 2 f w 5 2 f w 6 2 f w 7 2 f w 8 2 f w 9 2 f w 13 2 f w 2 f xt selector 5-bit counter selector prescaler selector intwt inttm3 selector f w 14 to 16-bit timer/ event counter 7 f xx/ 2 f xx f xx 5 f xx 6 f xx 7 2 f xx 8 2 f xx 9 2 f xx 11 2 intwdt maskable interrupt request reset intwdt non-maskable interrupt request prescaler selector control circuit 4 222 8-bit counter f xx 3 2
25 m pd78076, 78078 5.4 clock output control circuit this circuit can output clocks of the following frequencies: ? 19.5 khz/39.1 khz/78.1 khz/156 khz/313 khz/625 khz/1.25 mhz/2.5 mhz/5.0 mhz (at main system clock frequency of 5.0 mhz) ? 32.768 khz (at subsystem clock frequency of 32.768 khz) figure 5-7. clock output control circuit block diagram 5.5 buzzer output control circuit this circuit can output clocks of the following frequencies that can be used for driving buzzers: ? 1.2 khz/2.4 khz/4.9 khz/9.8 khz (at main system clock frequency of 5.0 mhz) figure 5-8. buzzer output control circuit block diagram pcl/p35 f xx /2 2 f xx /2 3 f xx /2 4 f xx /2 5 f xx /2 6 f xx /2 7 f xt synchronization circuit f xx /2 f xx selector output control circuit selector output control circuit buz/p36 f xx /2 9 f xx /2 10 f xx /2 11
26 m pd78076, 78078 5.6 a/d converter the a/d converter consists of eight 8-bit resolution channels. a/d conversion can be started by the following two methods: ? hardware starting ? software starting figure 5-9. a/d converter block diagram 5.7 d/a converter the d/a converter consists of two 8-bit resolution channels. the conversion method is the r-2r resistor ladder method. intp3/p03 tap selector ani0/p10 ani2/p12 ani3/p13 ani4/p14 ani5/p15 ani6/p16 ani7/p17 ani1/p11 av dd av ref0 av ss intad intp3 series resistor string selector sample & hold circuit voltage comparator successive approximation register (sar) edge detector control circuit a/d conversion result register (adcr) internal bus
27 m pd78076, 78078 5.8 serial interfaces there are the following three on-chip serial interface channels synchronous with the clock: ? serial interface channel 0 ? serial interface channel 1 ? serial interface channel 2 table 5-3. types and functions of serial interfaces function serial interface channel 0 serial interface channel 1 serial interface channel 2 3-wire serial i/o mode ? (msb/lsb first ? (msb/lsb first ? (msb/lsb first switching possible) switching possible) switching possible) 3-wire serial i/o mode with ? (msb/lsb first automatic data transmit/ switching possible) receive function 2-wire serial i/o mode ? (msb first) sbi mode ? (msb first) asynchronous serial (on-chip dedicated baud interface (uart) mode rate generator) n = 0, 1 m = 4, 5 x = 1, 2 figure 5-10. d/a converter block diagram internal bus selector d/a conversion value set register n (dacsn) av ref1 av ss d/a converter mode register damm inttm x dacsn write anon
28 m pd78076, 78078 figure 5-12. serial interface channel 1 block diagram figure 5-11. serial interface channel 0 block diagram internal bus buffer ram automatic data transmit/ receive address pointer (adtp) serial i/o shift register 1 (sio1) automatic data transmit/receive interval specification register (adti) match 5-bit counter selector handshake control circuit serial clock counter si1/p20 so1/p21 stb/p23 busy/p24 sck1/p22 intcsi1 f xx /2 to f xx /2 8 to2 interrupt request signal generator serial clock control circuit selector busy/acknowledge output circuit internal bus selector interrupt request signal generator to2 intcsi0 f xx /2 to f xx /2 8 si0/sb0/p25 so0/sb1/p26 sck0/p27 serial clock control circuit bus release/command/ acknowledge detector serial clock counter serial i/o shift register 0 (sio0) selector output latch
29 m pd78076, 78078 figure 5-13. serial interface channel 2 block diagram 5.9 real-time output port data set previously in the real-time output buffer is transferred to the output latch by hardware concurrently with timer interrupt request or external interrupt request generation in order to output to off-chip. this is a real- time output function. pins used to output to off-chip are called real-time output ports. by using a real-time output port, a signal which has no jitter can be output. this is most applicable to control of stepping motor, etc. figure 5-14. real-time output port block diagram receive buffer register (rxb/sio2) internal bus direction control circuit direction control circuit transmit shift register (txs/sio2) receive shift register (rxs) receive control circuit transmit control circuit sck output control circuit baud rate generator intser intst intsr/intcsi2 f xx to f xx /2 10 asck/sck2/p72 t x d/so2/p71 r x d/si2/p70 p127 p120 output trigger control circuit intp2 inttm1 inttm2 output latch real-time output buffer register lower 4 bits (rtbl) real-time output buffer register higher 4 bits (rtbh) internal bus real-time output port mode register (rtpm)
30 m pd78076, 78078 6. interrupt functions and test functions 6.1 interrupt functions a total of 24 interrupt sources are provided, divided into the following three types. ? non-maskable interrupt : 1 ? maskable interrupt : 22 ? software interrupt : 1 table 6-1. list of interrupt sources interrupt default interrupt source internal/ vector basic table configuration type priority name trigger external address type non- intwdt overflow of watchdog timer (when the watchdog internal 0004h (a) maskable timer mode 1 is selected) maskable 0 intwdt overflow of watchdog timer (when the interval (b) timer mode is selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h (d) 3 intp2 000ah 4 intp3 000ch 5 intp4 000eh 6 intp5 0010h 7 intp6 0012h 8 intcsi0 completion of serial interface channel 0 transfer internal 0014h (b) 9 intcsi1 completion of serial interface channel 1 transfer 0016h 10 intser occurrence of serial interface channel 2 uart 0018h reception error 11 intsr completion of serial interface channel 2 uart reception 001ah intcsi2 completion of serial interface channel 2 3-wire transfer 12 intst completion of serial interface channel 2 uart 001ch transmission 13 inttm3 reference interval signal from watch timer 001eh 14 inttm00 generation of matching signal of 16-bit timer register 0020h and capture/compare register (cr00) 15 inttm01 generation of matching signal of 16-bit timer register 0022h and capture/compare register (cr01) 16 inttm1 generation of matching signal of 8-bit timer/event 0024h counter 1 17 inttm2 generation of matching signal of 8-bit timer/event 0026h counter 2 18 intad completion of a/d conversion 0028h 19 inttm5 generation of matching signal of 8-bit timer/event 002ah counter 5 20 inttm6 generation of matching signal of 8-bit timer/event 002ch counter 6 software brk execution of brk instruction 003eh (e) notes 1. default priority is the priority order when several maskable interrupt requests are generated at the same time. 0 is the highest order and 20 is the lowest order. 2. basic configuration types (a) to (e) correspond to (a) to (e) in figure 6-1. note 1 note 2
31 m pd78076, 78078 figure 6-1. interrupt function basic configuration (1/2) (a) internal non-maskable interrupt (b) internal maskable interrupt (c) external maskable interrupt (intp0) interrupt request standby release signal internal bus vector table address generator priority control circuit mk ie pr isp if interrupt request internal bus priority control circuit vector table address generator standby release signal sampling clock select register (scs) if ie pr isp external interrupt mode register (intm0) sampling clock edge detector interrupt request internal bus mk priority control circuit vector table address generator standby release signal
32 m pd78076, 78078 (d) external maskable interrupt (except intp0) (e) software interrupt if : interrupt request flag e : interrupt enable flag isp : in-service priority flag mk : interrupt mask flag pr : priority specification flag figure 6-1. interrupt function basic configuration (2/2) if internal bus interrupt request edge detector vector table address generator standby release signal external interrupt mode register (intm0, intm1) mk ie pr isp priority control circuit internal bus interrupt request vector table address generator priority control circuit
33 m pd78076, 78078 6.2 test functions table 6-2 shows the two test functions available. table 6-2. test input factors test input factor internal/ name trigger external intwt overflow of watch timer internal intpt4 detection of falling edge of port 4 external figure 6-2. basic configuration of test function if : test input flag mk : test mask flag mk if internal bus standby release signal test input signal
34 m pd78076, 78078 7. external device expansion functions the external device expansion functions connect external devices to areas other than the internal rom, ram and sfr. external devices connection uses ports 4 to 6 and port 8. the external device expansion function has the following two modes: ? separate bus mode : external devices are connected by using an independent address bus and data bus. because an external latch circuit is not necessary, this mode is effective for reducing the number of components and the mounting area on a printed wiring board. ? multiplexed bus mode : external devices are connected by using a time-division multiplexed address/data bus. this mode can reduce the number of ports used when external devices are connected. 8. standby function the standby function is designed to reduce current consumption. it has the following two modes: ? halt mode : in this mode, the cpu operation clock is stopped. the average current consumption can be reduced by intermittent operation by combining this mode with the normal operation mode. ? stop mode : in this mode, oscillation of the main system clock is stopped. all the operations performed on the main system clock are suspended, and only the subsystem clock is used for extremely small power consumption. figure 8-1. standby function note current consumption can be reduced by shutting off the main system clock. if the cpu is operating on the subsystem clock, shut off the main system clock by setting mcc (bit 7 in the processor clock control register (pcc)). in this case, a stop instruction cannot be used. caution when switching on the main system clock again after the subsystem clock has been used with the main system clock stopped, be sure to provide enough time for oscillation stabilization with the program first. main system clock operation subsystem clock operation note interrupt request stop instruction stop mode (oscillation of the main system clock is stopped.) interrupt request interrupt request halt instruction halt mode (supply of clock to cpu is stopped although oscillation is retained.) halt instruction halt mode note (supply of clock to cpu is stopped although oscillation is retained.) css = 1 css = 0
35 m pd78076, 78078 9. reset function there are the following two reset methods. ? external reset input by reset pin ? internal reset by watchdog timer runaway time detection
36 m pd78076, 78078 10. instruction set (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz 2nd operand [hl + byte] #byte a r note sfr saddr !addr16 psw [de] [hl] [hl + b] $addr16 1 none 1st operand [hl + c] a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp b, c dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl + byte] mov [hl + b] [hl + c] x mulu c divuw note except r = a
37 m pd78076, 78078 (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw 2nd operand #word ax rp note sfrp saddrp !addr16 sp none 1st operand ax addw movw movw movw movw movw subw xchw cmpw rp movw movw note incw, decw push, pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr 2nd operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none 1st operand a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1 (4) call instructions/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz 2nd operand ax !addr16 !addr11 [addr5] $addr16 1st operand basic instruction br call callf callt br, bc br bnc bz, bnz compound instruction bt, bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
38 m pd78076, 78078 parameter symbol conditions ratings unit supply voltage v dd C0.3 to +7.0 v av dd C0.3 to v dd + 0.3 v av ref0 C0.3 to v dd + 0.3 v av ref1 C0.3 to v dd + 0.3 v av ss C0.3 to +0.3 v input voltage v i1 p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, C0.3 to v dd + 0.3 v p50 to p57, p64 to p67, p70 to p72, p80 to p87, p94 to p96, p100 to p103, p120 to p127, p130, p131, x1, x2, xt2, reset v i2 p60 to p63, p90 to p93 n-ch open-drain C0.3 to +16 v output voltage v o C0.3 to v dd + 0.3 v analog input voltage v an p10 to p17 analog input pin av ss C 0.3 to av ref0 + 0.3 v output leakage i oh per pin C10 ma current, high total for p30 to p37, p56, p57, p60 to p67, p90 to p96, C15 ma p100 to p103, p120 to p127 total for p01 to p06, p10 to p17, p20 to p27, p40 to C15 ma p47, p50 to p55, p70 to p72, p80 to p87, p130, p131 output leakage i ol note per pin peak value 30 ma current, low r.m.s. 15 ma total for p50 to p55 peak value 100 ma r.m.s. 70 ma total for p56, p57, p60 to p63 peak value 100 ma r.m.s. 70 ma total for p30 to p37, p64 to p67, p90 peak value 100 ma to p96, p100 to p103, p120 to p127 r.m.s. 70 ma total for p20 to p27, p40 to p47, peak value 50 ma p80 to p87 r.m.s. 20 ma total for p01 to p06, p10 to p17, peak value 50 ma p70 to p72, p130, p131 r.m.s 20 ma operating ambient t a C40 to +85 c temperature storage t stg C65 to +150 c temperature note the r.m.s. (root mean square) should be calculated as follows: [r.m.s.] = [peak value] ? duty caution product quality may suffer if the absolute maximum ratings are exceeded for even a single parameter or even momentarily. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark the characteristics of an alternate function pin are the same as those of port pins unless otherwise specified. 11. electrical specifications absolute maximum ratings (t a = 25 c)
39 m pd78076, 78078 input c in f = 1 mhz 15 pf capacitance unmeasured pins returned to 0 v. input/output c io f = 1 mhz p01 to p07, p10 to p17, 15 pf capacitance unmeasured pins returned to 0 v. p20 to p27, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p80 to p87, p94 to p96, p100 to p103, p120 to p127, p130, p131 p60 to p63, p90 to p93 20 pf remark the characteristics of an alternate function pin are the same as those of port pins unless otherwise specified. capacitance (t a = 25 c , v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit
40 m pd78076, 78078 parameter oscillation frequency (f x ) note 1 oscillation stabilization time note 2 oscillation frequency (f x ) note 1 oscillation stabilization time note 2 x1 input frequency (f x ) note 1 x1 input high/low-level width (t xh , t xl ) max. main system clock oscillator characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) resonator ceramic resonator crystal resonator external clock notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should always be the same as that of v ss . ? do not ground wiring to a ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. 2. when the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program. conditions v dd = oscillation voltage range after v dd reaches oscil- lation voltage range min. v dd = 4.5 to 5.5 v typ. unit min. recommended circuit 1.0 1.0 1.0 85 5.0 4 5.0 10 30 5.0 500 mhz ms mhz ms mhz ns ic x2 x1 c2 c1 x2 x1 pd74hcu04 m ic x2 x1 c2 c1 r1
41 m pd78076, 78078 parameter oscillation frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high/low-level width (t xth , t xtl ) subsystem clock oscillator characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd reaches oscillation voltage range min. cautions 1. when using the subsystem clock oscillator, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should always be the same as that of v ss . ? do not ground wiring to a ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. 2. the subsystem clock oscillator is designed to be a circuit with a low amplification level, for low power consumption more prone to malfunction due to noise than that of the main system clock. therefore, when using the subsystem clock, take special cautions for wiring methods. resonator crystal resonator external clock recommended circuit conditions v dd = 4.5 to 5.5 v min. typ. max. unit 32 32 5 32.768 1.2 35 2 10 100 15 m s khz s khz xt2 xt1 pd74hcu04 m ic xt2 xt1 c4 c3 r2
42 m pd78076, 78078 manufacturer part number frequency recommended circuit constant oscillation voltage range remarks c1 (pf) c2 (pf) r1 (k w ) min. (v) max. (v) tdk ccr1000k2 1.00 mhz 150 150 0 2.0 5.5 surface mount type ccr4.0mc3 4.00 mhz on-chip on-chip 0 1.8 5.5 on-chip capacitor surface mount type fcr4.0mc5 4.00 mhz on-chip on-chip 0 1.8 5.5 on-chip capacitor insertion type ccr5.00mc3 5.00 mhz on-chip on-chip 0 1.8 5.5 on-chip capacitor surface mount type fcr5.00mc5 5.00 mhz on-chip on-chip 0 2.0 5.5 on-chip capacitor insertion type murata mfg. csb1000j 1.00 mhz 100 100 5.6 2.2 5.5 insertion type corporation csa2.00mg040 2.00 mhz 100 100 0 1.9 5.5 insertion type cst2.00mg040 2.00 mhz on-chip on-chip 0 1.9 5.5 on-chip capacitor insertion type csa4.00mg 4.00 mhz 30 30 0 1.8 5.5 insertion type cst4.00mgw 4.00 mhz on-chip on-chip 0 1.8 5.5 on-chip capacitor insertion type csa5.00mg 5.00 mhz 30 30 0 2.0 5.5 insertion type cst5.00mgw 5.00 mhz on-chip on-chip 0 2.0 5.5 on-chip capacitor insertion type recommended oscillator constant main system clock : ceramic resonator (t a = C45 to +85 c) main system clock : ceramic resonator (t a = C20 to +80 c) manufacturer part number frequency recommended circuit constant oscillation voltage range remarks c1 (pf) c2 (pf) r1 (k w ) min. (v) max. (v) kyocera kbr-1000f 1.00 mhz 150 150 0 2.3 5.5 insertion type corporation kbr-2.0ms 2.00 mhz 82 82 0 2.4 5.5 insertion type pbrc4.00a 4.00 mhz 33 33 0 2.4 5.5 surface mount type pbrc4.00b 4.00 mhz on-chip on-chip 0 2.4 5.5 on-chip capacitor surface mount type kbr-4.00msa 4.00 mhz 33 33 0 2.4 5.5 insertion type kbr-4.00mks 4.00 mhz on-chip on-chip 0 2.4 5.5 on-chip capacitor insertion type pbrc5.00a 5.00 mhz 33 33 0 1.8 5.5 surface mount type pbrc5.00b 5.00 mhz on-chip on-chip 0 1.8 5.5 on-chip capacitor surface mount type kbr-5.00msa 5.00 mhz 33 33 0 1.8 5.5 insertion type kbr-5.00mks 5.00 mhz on-chip on-chip 0 1.8 5.5 on-chip capacitor insertion type caution the oscillator constant and oscillation voltage range indicate conditions of stable oscillation. the oscillation frequency precision is not guaranteed. for applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. for details, please contact directly the manufacturer of the resonator you will use.
43 m pd78076, 78078 parameter symbol conditions min. typ. max. unit input voltage, v ih1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 5.5 v 0.7v dd v dd v high p35 to p37, p40 to p47, p50 to p57, p64 to p67, p71, p80 to p87, p94 to p96, p102, p103, 0.8v dd v dd v p120 to p127, p130, p131 v ih2 p00 to p06, p20, p22, p24 to p27, v dd = 2.7 to 5.5 v 0.8v dd v dd v p33, p34, p70, p72, p100, p101, reset 0.85v dd v dd v v ih3 p60 to p63, p90 to p93 v dd = 2.7 to 5.5 v 0.7v dd 15 v (n-ch open-drain) 0.8v dd 15 v v ih4 x1, x2 v dd = 2.7 to 5.5 v v dd C 0.5 v dd v v dd C 0.2 v dd v v ih5 xt1/p07, xt2 4.5 v v dd 5.5 v 0.8v dd v dd v 2.7 v v dd < 4.5 v 0.9v dd v dd v note 0.9v dd v dd v input voltage, v il1 p10 to p17, p21, p23, p30 to p32, v dd = 2.7 to 5.5 v 0 0.3v dd v low p35 to p37, p40 to p47, p50 to p57, p64 to p67, p71, p80 to p87, p94 to p96, p102, p103, 0 0.2v dd v p120 to p127, p130, p131 v il2 p00 to p06, p20, p22, p24 to p27, v dd = 2.7 to 5.5 v 0 0.2v dd v p33, p34, p70, p72, p100, p101, reset 0 0.15v dd v v il3 p60 to p63, p90 to p93 4.5 v v dd 5.5 v 0 0.3v dd v (n-ch open-drain) 2.7 v v dd < 4.5 v 0 0.2v dd v 0 0.1v dd v v il4 x1, x2 v dd = 2.7 to 5.5 v 0 0.4 v 0 0.2 v v il5 xt1/p07, xt2 4.5 v v dd 5.5 v 0 0.2v dd v 2.7 v v dd < 4.5 v 0 0.1v dd v note 0 0.1v dd v output voltage, v oh v dd = 4.5 to 5.5 v, i oh = C1 ma v dd C 1.0 v high i oh = C100 m a v dd C 0.5 v output voltage, v ol1 p50 to p57, p60 to p63, v dd = 4.5 to 5.5 v, 0.4 2.0 v low p90 to p93 i ol = 15 ma p01 to p06, p10 to p17, p20 v dd = 4.5 to 5.5 v, 0.4 v to p27, p30 to p37, p40 to p47, i ol = 1.6 ma p64 to p67, p70 to p72, p80 to p87, p94 to p96, p100 to p103, p120 to p127, p130, p131 v ol2 sb0, sb1, sck0 v dd = 4.5 to 5.5 v, 0.2v dd v open-drain, at pulled-up (r = 1 k w ) v ol3 i ol = 400 m a 0.5 v dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) (1 of 3) note for use of p07/xt1 pin as p07, use an inverter to input the reverse phase of p07 to the xt2 pin . remark the characteristics of an alternate function pin are the same as those of port pins unless otherwise specified.
44 m pd78076, 78078 parameter symbol conditions min. typ. max. unit input leakage i lih1 v in = v dd p00 to p06, p10 to p17, p20 to p27, 3 m a current, high p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p80 to p87, p94 to p96, p100 to p103, p120 to p127, p130, p131, reset i lih2 x1, x2, xt1/p07, xt2 20 m a i lih3 v in = 15 v p60 to p63, p90 to p93 80 m a input leakage i lil1 v in = 0 v p00 to p06, p10 to p17, p20 to p27, C3 m a current, low p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72, p80 to p87, p94 to p96, p100 to p103, p120 to p127, p130, p131, reset i lil2 x1, x2, xt1/p07, xt2 C20 m a i lil3 p60 to p63, p90 to p93 C3 note 1 m a output leakage i loh v out = v dd 3 m a current, high output leakage i lol v out = 0 v C3 m a current, low mask option pull- r 1 v in = 0 v, p60 to p63, p90 to p93 20 40 90 k w up resistor software pull- r 2 v in = 0 v, 4.5 v v dd 5.5 v 15 40 90 k w up resistor note 2 p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50 to p57, p64 to p67, p70 to p72 , p80 to p87, p94 to p96, p100 to p103, p120 to p127, p130, p131 dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) (2 of 3) 2.7 v v dd < 4.5 v 20 500 k w notes 1. when the pull-up resistors are not connected to p60 to p63 and p90 to p93 (specified by mask option), a low-level input leakage current of C200 m a (max.) flows only for 1.5 clocks (without wait) after a read instruction has been executed to port 6 (p6), port mode register 6 (pm6), port 9 (p9), or port mode register 9 (pm9). at times other than this 1.5-clock interval, a C3 m a (max.) current flows. 2. a software pull-up resistor can be used only in the range of v dd = 2.7 to 5.5 v. remark the characteristics of an alternate function pin are the same as those of port pins unless otherwise specified.
45 m pd78076, 78078 v dd = 5.0 v 10% note 5 4.5 13.5 ma v dd = 3.0 v 10% note 6 0.7 2.1 ma v dd = 2.0 v 10% note 6 0.4 1.2 ma v dd = 5.0 v 10% note 5 8.0 24.0 ma v dd = 3.0 v 10% note 6 0.9 2.7 ma v dd = 5.0 v 10% 1.4 4.2 ma v dd = 3.0 v 10% 0.5 1.5 ma v dd = 2.0 v 10% 280 840 m a v dd = 5.0 v 10% 1.6 4.8 ma v dd = 3.0 v 10% 0.65 1.95 ma v dd = 5.0 v 10% 60 120 m a v dd = 3.0 v 10% 32 64 m a v dd = 2.0 v 10% 24 48 m a v dd = 5.0 v 10% 25 55 m a v dd = 3.0 v 10% 5 15 m a v dd = 2.0 v 10% 2.5 12.5 m a v dd = 5.0 v 10% 1 30 m a v dd = 3.0 v 10% 0.5 10 m a v dd = 2.0 v 10% 0.3 10 m a v dd = 5.0 v 10% 0.1 30 m a v dd = 3.0 v 10% 0.05 10 m a v dd = 2.0 v 10% 0.05 10 m a parameter symbol conditions min. typ. max. unit power supply current note 1 dc characteristics (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) (3 of 3) i dd3 32.768-khz crystal oscillation operating mode note 4 i dd4 32.768-khz crystal oscillation halt mode note 4 i dd5 xt1 = v dd stop mode when feedback resistor is used notes 1. refers to the current flowing to the v dd pin. the current flowing to the a/d converter, d/a converter, and ports is not included. 2. operation with main system clock f xx = f x /2 (when oscillation mode select register (osms) is set to 00h) 3. operation with main system clock f xx = f x (when oscillation mode select register (osms) is set to 01h) 4. when the main system clock operation is halted 5. operating in high-speed mode (when the processor clock control register (pcc) is set to 00h). 6. operating in low-speed mode (when the processor clock control register (pcc) is set to 04h). remark the characteristics of an alternate function pin are the same as those of port pins unless otherwise specified. i dd2 5.0-mhz crystal oscillation halt mode (f xx = 2.5 mhz) note 2 i dd1 5.0-mhz crystal oscillation operating mode (f xx = 2.5 mhz) note 2 5.0-mhz crystal oscillation operating mode (f xx = 5.0 mhz) note 3 5.0-mhz crystal oscillation halt mode (f xx = 5.0 mhz) note 3 i dd6 xt1 = v dd stop mode when feedback resistor is not used
46 m pd78076, 78078 parameter symbol conditions min. typ. max. unit cycle time t cy operating on main v dd = 2.7 to 5.5 v 0.8 64 m s (min. instruction system clock 2.0 64 m s execution time) 3.5 v v dd 5.5 v 0.4 32 m s 2.7 v v dd < 3.5 v 0.8 32 m s operating on subsystem clock 40 note 3 122 125 m s ti00 input high/ t tih00 , t til00 3.5 v v dd 5.5 v 2/f sam + 0.1 note 4 m s low-level width 2.7 v v dd < 3.5 v 2/f sam + 0.2 note 4 m s 2/f sam + 0.5 note 4 m s ti01 t tih01 , t til01 v dd = 2.7 to 5.5 v 10 m s input high/ low-level width 20 m s ti1, ti2, ti5, ti6 f ti1 v dd = 4.5 to 5.5 v 0 4 mhz input frequency 0 275 khz ti1, ti2, ti5, ti6 t tih1 , t til1 v dd = 4.5 to 5.5 v 100 ns input high/ low-level width 1.8 m s interrupt request t inth , t intl intp0 3.5 v v dd 5.5 v 2/f sam + 0.1 note 4 m s input high/low-level 2.7 v v dd < 3.5 v 2/f sam + 0.2 note 4 m s width 2/f sam + 0.5 note 4 m s intp1 to intp6, kr0 to kr7 v dd = 2.7 to 5.5 v 10 m s 20 m s reset low- t rsl v dd = 2.7 to 5.5 v 10 m s level width 20 m s ac characteristics (1) basic operation (t a = C40 to +85 c, v dd = 1.8 to 5.5 v) notes 1. when oscillation mode select register (osms) is set to 00h 2. when oscillation mode select register (osms) is set to 01h 3. the value when using external clock. when using crystal resonator, it is 114 m s (min.). 4. in combination with bits 0 (scs0) and 1 (scs1) of sampling clock select register (scs), selection of f sam is possible from f xx /2 n , f xx /32, f xx /64, and f xx /128 (when n = 0 to 4). remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency f xx = f x /2 note 1 f xx = f x note 2
47 m pd78076, 78078 t cy vs v dd (at f xx = f x main system clock operation) t cy vs v dd (at f xx = f x /2 main system clock operation) 60 cycle time t cy [ s] 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] operation guaranteed range m 60 cycle time t cy [ s] 10 2.0 1.0 0.5 0.4 0 1234 56 supply voltage v dd [v] operation guaranteed range m
48 m pd78076, 78078 parameter symbol conditions min. max. unit astb high-level width t asth 0.85t cy C 50 ns address setup time t ads 0.85t cy C 50 ns address hold time t adh 50 ns data input time from address t add1 (2.85 + 2n)t cy C 80 ns t add2 (4 + 2n)t cy C 100 ns data input time from rd t rdd1 (2 + 2n)t cy C 100 ns t rdd2 (2.85 + 2n)t cy C 100 ns read data hold time t rdh 0ns rd low-level width t rdl1 (2 + 2n)t cy C 60 ns t rdl2 (2.85 + 2n)t cy C 60 ns wait input time from rd t rdwt1 0.85t cy C 50 ns t rdwt2 2t cy C 60 ns wait input time from wr t wrwt 2t cy C 60 ns wait low-level width t wtl (1.15 + 2n)t cy (2 + 2n)t cy ns write data setup time t wds (2.85 + 2n)t cy C 100 ns write data hold time t wdh load resistance 3 5 k w 20 ns wr low-level width t wrl (2.85 + 2n)t cy C 60 ns rd delay time from astb t astrd 25 ns wr delay time from astb t astwr 0.85t cy + 20 ns astb - delay time from t rdast 0.85t cy C 10 1.15t cy + 20 ns rd - at external fetch address hold time from t rdadh 0.85t cy C 50 1.15t cy + 50 ns rd - at external fetch write data output time from rd - t rdwd 40 ns write data output time from wr t wrwd 050ns address hold time from wr - 0.85t cy C 20 1.15t cy + 40 ns rd - delay time from wait - t wtrd 1.15t cy + 40 3.15t cy + 40 ns wr - delay time from wait - t wtwr 1.15t cy + 30 3.15t cy + 30 ns (2) read/write operation t wradh remarks 1. mcs: bit 0 of the oscillation mode select register (osms) 2. pcc2 to pcc0: bits 2 to 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits. (a) when mcs = 1, pcc2 to pcc0 = 000b (t a = C40 to + 85 c, v dd = 4.5 to 5.5 v)
49 m pd78076, 78078 (b) except when mcs = 1, pcc2 to pcc0 = 000b (t a = e40 to +85 c, v dd = 2.7 to 5.5 v) parameter symbol conditions min. max. unit astb high-level width t asth t cy C 80 ns address setup time t ads t cy C 80 ns address hold time t adh 0.4t cy C 10 ns data input time from address t add1 (3 + 2n)t cy C 160 ns t add2 (4 + 2n)t cy C 200 ns data input time from rd t rdd1 (1.4 + 2n)t cy C 70 ns t rdd2 (2.4 + 2n)t cy C 70 ns read data hold time t rdh 0ns rd low-level width t rdl1 (1.4 + 2n)t cy C 20 ns t rdl2 (2.4 + 2n)t cy C 20 ns wait input time from rd t rdwt1 t cy C 100 ns t rdwt2 2t cy C 100 ns wait input time from wr t wrwt 2t cy C 100 ns wait low-level width t wtl (1 + 2n)t cy (2 + 2n)t cy ns write data setup time t wds (2.4 + 2n)t cy C60 ns write data hold time t wdh load resistance 3 5 k w 20 ns wr low-level width t wrl (2.4 + 2n)t cy C 20 ns rd delay time from astb t astrd 0.4t cy C 30 ns wr delay time from astb t astwr 1.4t cy C 30 ns astb - delay time from t rdast t cy C10 t cy + 20 ns rd - at external fetch address hold time from t rdadh t cy C 80 t cy + 50 ns rd - at external fetch write data output time from rd - t rdwd 0.4t cy C 30 ns write data output time from wr t wrwd 060ns address hold time from wr - t wradh t cy C 60 t cy + 60 ns rd - delay time from wait - t wtrd 0.6t cy + 180 2.6t cy + 180 ns wr - delay time from wait - t wtwr 0.6t cy + 120 2.6t cy + 120 ns remarks 1. mcs: bit 0 of the oscillation mode select register (osms) 2. pcc2 to pcc0: bits 2 to 0 of the processor clock control register (pcc) 3. t cy = t cy /4 4. n indicates the number of waits.
50 m pd78076, 78078 (3) serial interface (t a = e40 to +85 c, v dd = 1.8 to 5.5 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0... internal clock output) note c is the load capacitance of so0 output line. (ii) 3-wire serial i/o mode (sck0... external clock input) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy2 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck0 high/low-level t kh2 , t kl2 4.5 v v dd 5.5 v 400 ns width 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1600 ns 2400 ns si0 setup time t sik2 v dd = 2.0 to 5.5 v 100 ns (to sck0 - ) 150 ns si0 hold time t ksi2 400 ns (from sck0 - ) so0 output delay time t kso2 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns from sck0 500 ns sck0 rise/fall time t r2 , t f2 when using external device 160 ns expansion function when not using external 1000 ns device expansion function note c is the load capacitance of the so0 output line. parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy1 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck0 high/low-level t kh1 , t kl1 v dd = 4.5 to 5.5 v t kcy1 /2 C 50 ns width t kcy1 /2 C 100 ns si0 setup time t sik1 4.5 v v dd 5.5 v 100 ns (to sck0 - ) 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si0 hold time t ksi1 400 ns (from sck0 - ) so0 output delay time t kso1 c = 100 pf note 300 ns from sck0
51 m pd78076, 78078 (iii) sbi mode (sck0... internal clock output) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy3 4.5 v v dd 5.5 v 800 ns 2.0 v v dd < 4.5 v 3200 ns 4800 ns sck0 high/low-level t kh3 ,v dd = 4.5 to 5.5 v t kcy3 /2 C 50 ns width t kl3 t kcy3 /2 C 150 ns sb0, sb1 setup time t sik3 4.5 v v dd 5.5 v 100 ns (to sck0 -) 2.0 v v dd < 4.5 v 300 ns 400 ns sb0, sb1 hold time t ksi3 t kcy3 /2 ns (from sck0 - ) sb0, sb1 output delay t kso3 r = 1 k w v dd = 4.5 to 5.5 v 0 250 ns time from sck0 c = 100 pf note 0 1000 ns sb0, sb1 from sck0 - t ksb t kcy3 ns sck0 from sb0, sb1 t sbk t kcy3 ns sb0, sb1 high-level width t sbh t kcy3 ns sb0, sb1 low-level width t sbl t kcy3 ns note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines, respectively. (iv) sbi mode (sck0... external clock input) parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy4 4.5 v v dd 5.5 v 800 ns 2.0 v v dd < 4.5 v 3200 ns 4800 ns sck0 high/low-level t kh4 , 4.5 v v dd 5.5 v 400 ns width t kl4 2.0 v v dd < 4.5 v 1600 ns 2400 ns sb0, sb1 setup time t sik4 4.5 v v dd 5.5 v 100 ns (to sck0 -) 2.0 v v dd < 4.5 v 300 ns 400 ns sb0, sb1 hold time t ksi4 t kcy4 /2 ns (from sck0 - ) sb0, sb1 output delay t kso4 r = 1 k w v dd = 4.5 to 5.5 v 0 300 ns time from sck0 c = 100 pf note 0 1000 ns sb0, sb1 from sck0 - t ksb t kcy4 ns sck0 from sb0, sb1 t sbk t kcy4 ns sb0, sb1 high-level width t sbh t kcy4 ns sb0, sb1 low-level width t sbl t kcy4 ns sck0 rise/fall time t r4 , t f4 when using external device 160 ns expansion function when not using external device 1000 ns expansion function note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines, respectively.
52 m pd78076, 78078 parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy5 r = 1 k w , 2.7 v v dd 5.5 v 1600 ns c = 100 pf note 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck0 high-level width t kh5 v dd = 2.7 to 5.5 v t kcy5 /2 C 160 ns t kcy5 /2 C 190 ns sck0 low-level width t kl5 v dd = 4.5 to 5.5 v t kcy5 /2 C 50 ns t kcy5 /2 C 100 ns sb0, sb1 setup time t sik5 4.5 v v dd 5.5 v 300 ns (to sck0 -) 2.7 v v dd < 4.5 v 350 ns 2.0 v v dd < 2.7 v 400 ns 500 ns sb0, sb1 hold time t ksi5 600 ns (from sck0 - ) sb0, sb1 output delay t kso5 0 300 ns time from sck0 (v) 2-wire serial i/o mode (sck0... internal clock output) note r and c are the load resistance and load capacitance of the sck0, sb0, and sb1 output lines, respectively. parameter symbol conditions min. typ. max. unit sck0 cycle time t kcy6 2.7 v v dd 5.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck0 high-level width t kh6 2.7 v v dd 5.5 v 650 ns 2.0 v v dd < 2.7 v 1300 ns 2100 ns sck0 low-level width t kl6 2.7 v v dd 5.5 v 800 ns 2.0 v v dd < 2.7 v 1600 ns 2400 ns sb0, sb1 setup time t sik6 v dd = 2.0 to 5.5 v 100 ns (to sck0 -) 150 ns sb0, sb1 hold time t ksi6 t kcy6 /2 ns (from sck0 - ) sb0, sb1 output delay t kso6 r = 1 k w , 4.5 v v dd 5.5 v 0 300 ns time from sck0 c = 100 pf note 2.0 v v dd < 4.5 v 0 500 ns 800 ns sck0 rise/fall time t r6 , t f6 when using external device 160 ns expansion function when not using external device 1000 ns expansion function (vi) 2-wire serial i/o mode (sck0... external clock input) note r and c are the load resistance and load capacitance of the sb0 and sb1 output lines, respectively.
53 m pd78076, 78078 parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy8 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck1 high/low-level t kh8 , 4.5 v v dd 5.5 v 400 ns width t kl8 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1600 ns 2400 ns si1 setup time t sik8 v dd = 2.0 to 5.5 v 100 ns (to sck1 - ) 150 ns si1 hold time t ksi8 400 ns (from sck1 - ) so1 output delay time t kso8 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns from sck1 500 ns sck1 rise/fall time t r8 , t f8 when using external device 160 ns expansion function when not using external device 1000 ns expansion function parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy7 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck1 high/low-level t kh7 , t kl7 v dd = 4.5 to 5.5 v t kcy7 /2 C 50 ns width t kcy7 /2 C 100 ns si1 setup time t sik7 4.5 v v dd 5.5 v 100 ns (to sck1 - ) 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si1 hold time t ksi7 400 ns (from sck1 - ) so1 output delay time t kso7 c = 100 pf note 300 ns from sck1 (b) serial interface channel 1 (i) 3-wire serial i/o mode (sck1... internal clock output) note c is the load capacitance of the so1 output line. (ii) 3-wire serial i/o mode (sck1... external clock input) note c is the load capacitance of the so1 output line.
54 m pd78076, 78078 parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy9 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck1 high/low-level t kh9 , t kl9 v dd = 4.5 to 5.5 v t kcy9 /2 C 50 ns width t kcy9 /2 C 100 ns si1 setup time t sik9 4.5 v v dd 5.5 v 100 ns (to sck1 - ) 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si1 hold time t ksi9 400 ns (from sck1 - ) so1 output delay time t kso9 c = 100 pf note 300 ns from sck1 stb - from sck1 - t sbd t kcy9 /2 C 100 t kcy9 /2 + 100 ns strobe signal t sbw 2.7 v v dd 5.5 v t kcy9 C 30 t kcy9 + 30 ns high-level width 2.0 v v dd < 2.7 v t kcy9 C 60 t kcy9 + 60 ns t kcy9 C 90 t kcy9 + 90 ns busy signal setup time t bys 100 ns (to busy signal detection timing) busy signal hold time t byh 4.5 v v dd 5.5 v 100 ns (from busy signal 2.7 v v dd < 4.5 v 150 ns detection timing) 2.0 v v dd < 2.7 v 200 ns 300 ns sck1 from busy t sps 2t kcy9 ns inactive (iii) 3-wire serial i/o mode with automatic transmit/receive function (sck1... internal clock output) note c is the load capacitance of the so1 output line.
55 m pd78076, 78078 parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy10 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck1 high/low-level t kh10 , 4.5 v v dd 5.5 v 400 ns width t kl10 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1600 ns 2400 ns si1 setup time t sik10 v dd = 2.0 to 5.5 v 100 ns (to sck1 - ) 150 ns si1 hold time t ksi10 400 ns (from sck1 - ) so1 output delay time t kso10 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns from sck1 500 ns sck1 rise/fall time t r10 , t f10 when using external device 160 ns expansion function when not using external device 1000 ns expansion function (iv) 3-wire serial i/o mode with automatic transmit/receive function (sck1... external clock input) note c is the load capacitance of the so1 output line.
56 m pd78076, 78078 parameter symbol conditions min. typ. max. unit sck2 cycle time t kcy12 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck2 high/low-level t kh12 , 4.5 v v dd 5.5 v 400 ns width t kl12 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1600 ns 2400 ns si2 setup time t sik12 v dd = 2.0 to 5.5 v 100 ns (to sck2 - ) 150 ns si2 hold time t ksi12 400 ns (from sck2 - ) so2 output delay time t kso12 c = 100 pf note v dd = 2.0 to 5.5 v 300 ns from sck2 500 ns sck2 rise/fall time t r12 , t f12 v dd = 4.5 to 5.5 v 1000 ns when not using external device expansion function 160 ns parameter symbol conditions min. typ. max. unit sck2 cycle time t kcy11 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns sck2 high/low-level t kh11 , t kl11 v dd = 4.5 to 5.5 v t kcy11 /2 C 50 ns width t kcy11 /2 C 100 ns si2 setup time t sik11 4.5 v v dd 5.5 v 100 ns (to sck2 - ) 2.7 v v dd < 4.5 v 150 ns 2.0 v v dd < 2.7 v 300 ns 400 ns si2 hold time t ksi11 400 ns (from sck2 - ) so2 output delay time t kso11 c = 100 pf note 300 ns from sck2 (c) serial interface channel 2 (i) 3-wire serial i/o mode (sck2... internal clock output) note c is the load capacitance of so2 output line. (ii) 3-wire serial i/o mode (sck2... external clock input) note c is the load capacitance of the so2 output line.
57 m pd78076, 78078 parameter symbol conditions min. typ. max. unit asck cycle time t kcy13 4.5 v v dd 5.5 v 800 ns 2.7 v v dd < 4.5 v 1600 ns 2.0 v v dd < 2.7 v 3200 ns 4800 ns asck high/low-level t kh13 , t kl13 4.5 v v dd 5.5 v 400 ns width 2.7 v v dd < 4.5 v 800 ns 2.0 v v dd < 2.7 v 1600 ns 2400 ns transfer rate 4.5 v v dd 5.5 v 39063 bps 2.7 v v dd < 4.5 v 19531 bps 2.0 v v dd < 2.7 v 9766 bps 6510 bps asck rise/fall time t r13 , t f13 v dd = 4.5 to 5.5 v 1000 ns when not using external device expansion function 160 ns (iii) uart mode (dedicated baud rate generator output) parameter symbol conditions min. typ. max. unit transfer rate 4.5 v v dd 5.5 v 78125 bps 2.7 v v dd < 4.5 v 39063 bps 2.0 v v dd < 2.7 v 19531 bps 9766 bps (iv) uart mode (external clock input)
58 m pd78076, 78078 ac timing test points (excluding x1, xt1 inputs) ti timing clock timing 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points t xl t xh 1/f x v ih4 (min.) v il4 (max.) t xtl t xth 1/f xt v ih5 (min.) v il5 (max.) x1 input xt1 input t til00 , t til01 t tih00 , t tih01 ti00, ti01 ti1, ti2, ti5, ti6 1/f ti1 t tih1 t til1
59 m pd78076, 78078 read/write operation external fetch (no wait) : remark ( ) is valid only in the separate bus mode. external fetch (wait insertion) : remark ( ) is valid only in the separate bus mode. t asth t adh t add1 hi-z t ads t rdd1 t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 (a0 to a7) ad0 to ad7 astb rd upper (lower) 8-bit address operation code lower 8-bit address t asth t adh t add1 hi-z t ads t rdadh t rdast t astrd t rdl1 t rdh a8 to a15 (a0 to a7) ad0 to ad7 astb rd t wtrd t wtl t rdwt1 wait t rdd1 upper (lower) 8-bit address operation code lower 8-bit address
60 m pd78076, 78078 remark ( ) is valid only in the separate bus mode. external data access (wait insertion) : remark ( ) is valid only in the separate bus mode. external data access (no wait) : t astrd t asth t adh t add2 hi-z t ads t rdl2 a8 to a15 (a0 to a7) ad0 to ad7 astb rd t wds t wrl wr t rdh hi-z hi-z t wrwd t astwr t wradh upper (lower) 8-bit address write data read data lower 8-bit address t rdd2 t wdh t rdwd t astrd t asth t adh t add2 hi-z t ads t rdl2 a8 to a15 (a0 to a7) ad0 to ad7 astb rd t wds t wrl wr t rdh hi-z hi-z t wrwd t astwr t wradh upper (lower) 8-bit address write data read data lower 8-bit address t rdd2 t wdh t rdwt2 t wtl t wrwt t wtwr t wtl wait t wtrd t rdwd
61 m pd78076, 78078 serial transfer timing 3-wire serial i/o mode : t kcym t klm t khm sck0 to sck2 si0 to si2 so0 to so2 t sikm t ksim t ksom input data output data t rn t fn sck0 sb0, sb1 t ksb t sbl t sbh t sbk t kso3, 4 t ksi3, 4 t sik3, 4 t f4 t r4 t kl3, 4 t kh3, 4 t kcy3, 4 sck0 sb0, sb1 t ksb t sbk t kso3, 4 t ksi3, 4 t sik3, 4 t f4 t r4 t kl3, 4 t kh3, 4 t kcy3, 4 m = 1, 2, 7, 8, 11, 12 n = 2, 8, 12 sbi mode (bus release signal transfer) : sbi mode (command signal transfer) :
62 m pd78076, 78078 2-wire serial i/o mode : 3-wire serial i/o mode with automatic transmit/receive function : 3-wire serial i/o mode with automatic transmit/receive function (busy processing) : note the signal is not actually driven low here; it is shown as such to indicate the timing. t kso5, 6 t sik5, 6 t kcy5, 6 t kl5, 6 t kh5, 6 sck0 t ksi5, 6 sb0, sb1 t f6 t r6 t sbw t sbd t kcy9, 10 t kh9, 10 t ksi9, 10 t kso9, 10 t sik9, 10 d2 d1 d0 d7 d7 d2 d1 d0 so1 si1 sck1 stb t r10 t kl9, 10 t f10 t bys sck1 t sps busy (active high) 789 note 10 note 10+n note 1 t byh
63 m pd78076, 78078 parameter symbol conditions min. typ. max. unit 8 bit r = 2 m w note 1 1.2 % r = 4 m w note 1 0.8 % r = 10 m w note 1 0.6 % note 4.5 v av ref1 5.5 v 10 m s c=30pf 2.7 v av ref1 < 4.5 v 15 m s 1.8 v av ref1 < 2.7 v 20 m s r o note 2 10 k w av ref1 1.8 v dd v r airef1 dacs0, dacs1 = 55h note 2 48 k w resolution overall error settling time output resistance analog reference voltage resistance between av ref1 and av ss a/d converter characteristics (t a = C40 to +85 c, av dd = v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) uart mode (external clock input) : d/a converter characteristics (t a = e40 to +85 c, v dd = 1.8 to 5.5 v, av ss = v ss = 0 v) note excluding quantization error ( 1/2 lsb). it is indicated as a ratio to the full-scale value. remarks 1. f xx : main system clock frequency (f x or f x /2) 2. f x : main system clock oscillation frequency parameter symbol conditions min. typ. max. unit 8 8 8 bit 2.7 v av ref0 av dd 0.6 % 1.8 v av ref0 < 2.7 v 1.4 % t conv 2.0 v av dd 5.5 v 19.1 200 m s 1.8 v av dd < 2.0 v 38.2 200 m s t samp 12/f xx m s v ian av ss av ref0 v av ref0 1.8 av dd v r airef0 4 14 k w resolution overall error note conversion time sampling time analog input voltage reference voltage resistance between av ref0 and av ss notes 1. r and c are the d/a converter output pin load resistance and load capacitance, respectively. 2. value for one d/a converter channel remark dacs0, dacs1: d/a conversion value setting registers 0, 1. t kcy13 t kh13 t kl13 t f13 t r13 asck
64 m pd78076, 78078 data memory stop mode low supply voltage data retention characteristics (t a = e40 to +85 c) note in combination with bits 0 to 2 (osts0 to osts2) of oscillation stabilization time select register (osts), selection is possible from 2 12 /f xx and 2 14 /f xx to 2 17 /f xx . parameter symbol conditions min. typ. max. unit data retention power v dddr 1.8 5.5 v supply voltage data retention i dddr v dddr = 1.8 v 0.1 10 m a power supply subsystem clock stop and feed- current back resistor disconnected release signal set time t srel 0 m s oscillation stabilization t wait release by reset 2 17 /fx ms wait time release by interrupt request note ms remark f xx : main system clock frequency (f x or f x /2) f x : main system clock oscillation frequency data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt request signal) t srel t wait v dd reset stop mode data retention mode internal reset operation halt mode operating mode v dddr stop instruction execution t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr
65 m pd78076, 78078 interrupt request input timing reset input timing t intl t inth intp0 to intp6 t rsl reset
66 m pd78076, 78078 12. characteristic curves (reference value) i dd vs v dd (fx = fxx = 5.0 mhz) (t a = 25?c) pcc = 01h pcc = 00h pcc = 02h pcc = 03h pcc = 04h pcc = 30h halt (x1 oscillation, xt1 oscillation) pcc = b0h halt (x1 stop, xt1 oscillation) 02345678 0.001 0.005 0.01 0.05 0.1 1.0 5.0 10.0 supply voltage v dd (v) supply current i dd (ma) 0.5
67 m pd78076, 78078 i dd vs v dd (fx = 5.0 mhz, fxx = 2.5 mhz) (t a = 25?c) 0 0.001 0.005 0.01 0.05 0.1 1.0 5.0 10.0 supply voltage v dd (v) supply current i dd (ma) 0.5 2345678 pcc = b0h halt (x1 stop, xt1 oscillation) halt (x1 oscillation, xt1 oscillation) pcc = 02h pcc = 03h pcc = 30h pcc = 04h pcc = 01h pcc = 00h
68 m pd78076, 78078 v dd = 5 v v dd = 4 v v dd = 3 v v dd = 2 v i ol vs v ol (port 0) low-level output voltage v ol [v] 0 0 0.5 1.0 1.5 10 low-level output current i ol [ma] (t a = 25?) 20 30 v dd = 5 v v dd = 4 v v dd = 3 v v dd = 2 v i oh vs v oh (port 0) v dd ?v oh [v] 0 0 0.5 1.0 1.5 5 10 high-level output current i oh [ma] (t a = 25?)
69 m pd78076, 78078 0 0 0.5 1.0 1.5 10 20 30 low-level output voltage v ol [v] low-level output current i ol [ma] i ol vs v ol (port 3) v dd = 5 v v dd = 4 v v dd = 3 v v dd = 2 v (t a = 25?) v dd = 5 v v dd = 4 v v dd = 3 v v dd = 2 v i oh vs v oh (port 3) 0 0 0.5 1.0 1.5 5 10 high-level output current i oh [ma] (t a = 25?) v dd ?v oh [v]
70 m pd78076, 78078 i ol vs v ol (port 6) low-level output voltage v ol [v] 0 0 0.5 1.0 1.5 10 low-level output current i ol [ma] (t a = 25?) 20 30 v dd = 2 v v dd = 3 v v dd = 4 v v dd = 5 v
71 m pd78076, 78078 remark the external dimensions and material of the es version are the same as that of the mass-produced version. 13. package drawings 100 pin plastic qfp (14x20) item millimeters inches note each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. p100gf-65-3ba1-3 b 20.0?.2 0.795 +0.009 ?.008 c 14.0?.2 0.551 +0.009 ?.008 d 17.6?.4 0.693?.016 f 0.8 0.031 g 0.6 0.024 h 0.30?.10 0.012 i 0.15 0.006 j 0.65 (t.p.) 0.026 (t.p.) k 1.8?.2 0.071 +0.008 ?.009 l 0.8?.2 0.031 n 0.10 0.004 q 0.1?.1 0.004?.004 s 3.0 max. 0.119 max. detail of lead end r q j k m l n p g f h i m p 2.7?.1 0.106 +0.005 ?.004 80 81 50 100 1 31 30 51 b a cd s a 23.6?.4 0.929?.016 m 0.15 0.006 +0.10 ?.05 r5 ? 5 ? +0.004 ?.005 +0.009 ?.008 +0.004 ?.003
72 m pd78076, 78078 100 pin plastic qfp (fine pitch) ( 14) item millimeters inches i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) a note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. s a 16.0?.2 0.630?.008 b 14.0?.2 0.551 +0.009 ?.008 c 14.0?.2 0.551 +0.009 ?.008 d 16.0?.2 0.630?.008 f g 1.0 1.0 0.039 0.039 h 0.22 0.009?.002 p100gc-50-7ea-2 k 1.0?.2 0.039 +0.009 ?.008 l 0.5?.2 0.020 +0.008 ?.009 m 0.17 0.007 n 0.10 0.004 p 1.45 0.057 +0.05 ?.04 +0.03 ?.07 b c d j h i g f p n l k m q r detail of lead end q 0.125?.075 0.005?.003 r s 1.7 max. 55 55 0.067 max. +0.001 ?.003 m 1 25 26 50 100 76 75 51 remark the external dimensions and material of the es version are the same as that of the mass-produced version.
73 m pd78076, 78078 remark the external dimensions and material of the es version are the same as that of the mass-produced version. 100 pin plastic lqfp (fine pitch) (14 14) item millimeters inches note each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. s100gc-50-8eu f 1.00 0.039 b 14.00?.20 0.551 +0.009 ?.008 s 1.60 max. 0.063 max. l 0.50?.20 0.020 +0.008 ?.009 +0.009 ?.008 c 14.00?.20 0.551 +0.009 ?.008 a 16.00?.20 0.630?.008 g 1.00 0.039 h 0.22 0.009?.002 i 0.08 0.003 j 0.50 (t.p.) 0.020 (t.p.) k 1.00?.20 0.039 +0.009 ?.008 n 0.08 0.003 p 1.40?.05 0.055?.002 r3 3 +7 ? +7 ? d 16.00?.20 0.630?.008 m q r k m l j h i f g p n detail of lead end m 0.17 0.007 +0.001 ?.003 +0.03 ?.07 q 0.10?.05 0.004?.002 +0.05 ?.04 1 25 26 50 100 76 75 51 cd s a b
74 m pd78076, 78078 14. recommended soldering conditions the m pd78076 and 78078 should be soldered and mounted under the conditions recommended in the table below. for detail of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, consult an nec sales personnel. table 14-1. surface mounting type soldering conditions (1) m pd78076gf- -3ba: 100-pin plastic qfp (14 20 mm, resin thickness 2.7 mm) m pd78078gf- -3ba: 100-pin plastic qfp (14 20 mm, resin thickness 2.7 mm) soldering soldering conditions recommended method condition symbol infrared reflow package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), ir35-00-3 number of times: three or less. vps package peak temperature: 215 c, duration: 40 sec. max. (at 200 c or above), vp15-00-3 number of times: three or less. wave soldering bath temperature: 260 c max., duration: 10 sec. max., number of ws60-00-1 soldering times: once, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max. duration: 3 sec. max. (per pin row) (2) m pd78076gc- -7ea: 100-pin plastic qfp (fine pitch) (14 14 mm, resin thickness 1.45 mm) m pd78078gc- -7ea: 100-pin plastic qfp (fine pitch) (14 14 mm, resin thickness 1.45 mm) soldering soldering conditions recommended method condition symbol infrared reflow package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), ir35-107-2 number of times: two or less. exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 10 hours) vps package peak temperature: 215 c, duration: 40 sec. max. (at 200 c or above), vp15-107-2 number of times: two or less. exposure limit: 7 days note (after that, prebaking is necessary at 125 c for 10 hours) partial heating pin temperature: 300 c max. duration: 3 sec. max. (per pin row) note exposure limit after dry-pack is opened. storage conditions: temperature of 25 c and relative humidity of 65% or less. cautions 1. use of more than one soldering method should be avoided (except for the partial heating method). 2. the soldering conditions for the m pd78076gc-xxx-8eu and m pd78078gc-xxx-8eu are unde- fined, since they are still under development.
75 m pd78076, 78078 appendix a. development tools the following tools are available for system development using the m pd78076 and 78078. also refer to (5) cautions when using development tools . (1) language processing software ra78k/0 assembler package common to the 78k/0 series cc78k/0 c compiler package common to the 78k/0 series df78078 device file common to the m pd78078 subseries cc78k/0Cl c compiler library source file common to the 78k/0 series (2) prom writing tools pg-1500 prom programmer pa-78p078gf programmer adapters connected to the pg-1500 pa-78p078gc pa-78p078kl-t pg-1500 controller pg-1500 control program (3) debugging tools ? in-circuit emulator (when ie-78k0-ns is used) ie-78k0-ns note in-circuit emulator common to the 78k/0 series ie-70000-mc-ps-b power supply unit for the ie-78k0-ns ie-70000-98-if-c note interface adapter when using the pc-9800 series (except for notebook computers) as the host machine ie-70000-cd-if note pc card and interface cable when using the pc-9800 series notebook computers as the host machine ie-70000-pc-if-c note interface adapter when using ibm pc/at? and its compatibles as the host machine ie-78078-ns-em1 note emulation board to common to the m pd78078 subseries np-100gc emulation probe for 100-pin plastic qfp (gc-8eu type) np-100gf emulation probe for 100-pin plastic qfp (gf-3ba type) tgc-100sdw conversion adapter to connect the np-100gc and the target system board on which 100-pin plastic qfp (gc-8eu type) can be mounted ev-9200gf-100 socket mounted on the target system board for 100-pin plastic qfp (gf-3ba type) id78k0-ns note integrated debugger for the ie-78k0-ns sm78k0 system simulator common to the 78k/0 series df78078 device file common to the m pd78078 subseries note under development
76 m pd78076, 78078 in-circuit emulator (when ie-78001-r-a is used) ie-78001-r-a note in-circuit emulator common to the 78k/0 series ie-70000-98-if-b interface adapter when using the pc-9800 series (except for notebook computers) ie-70000-98-if-c note as the host machine ie-70000-pc-if-b interface adapter and cable when using ibm pc/at and its compatibles as the host ie-70000-pc-if-c note machine ie-78000-r-sv3 interface adapter and cable when using ews as the host machine ie-78078-ns-em1 note emulation board common to the m pd78078 subseries ie-78078-r-em ie-78k0-r-ex1 note emulation probe conversion board that is necessary when using the ie-78078-ns-em1 on the ie-78001-r-a ep-78064gc-r emulation probe for 100-pin plastic qfp (gc-8eu type) ep-78064gf-r emulation probe for 100-pin plastic qfp (gf-3ba type) tgc-100sdw conversion adapter to connect the ep-78064gc-r and the target system board on which 100-pin plastic qfp (gc-8eu type) can be mounted ev-9200gf-100 socket mounted on the target system board for 100-pin plastic qfp (gf-3ba type) id78k0 integrated debugger for the ie-78001-r-a sm78k0 system simulator common to the 78k/0 series df78078 device file common to the m pd78078 subseries note under development (4) real-time os rx78k/0 real-time os for the 78k/0 series mx78k0 os for the 78k/0 series
77 m pd78076, 78078 (5) cautions when using development tools ? the id78k0-ns, id78k0, and sm78k0 are used in combination with the df78078. ? the cc78k/0 and rx78k/0 are used in combination with the ra78k/0 or df78078. ? the np-100gc and np-100gf are products of naito densei machidaseisakusho co., ltd. (044-822- 3813). contact an nec distributor about purchasing. ? the tgc-100sdw is a product of tokyo eletech corporation. refer to: daimaru kogyo, ltd. tokyo electronic components division (03-3820-7112) osaka electronic components division (06-244-6672) ? refer to 78k/0 series selection guide (u11126e) about third-party development tools. ? the host machine and the os applied to each software are shown below. host machine pc ews [os] pc-9800 series [windows?] hp9000 series 700 tm [hp-ux tm ] ibm pc/at and compatibles [japanese/english windows] sparcstation tm [sunos tm ] software news tm (risc) [news-os tm ] ra78k/0 ? note ? cc78k/0 ? note ? pg-1500 controller ? note C id78k0-ns ? C id78k0 ?? sm78k0 ? C rx78k/0 ? note ? mx78k0 ? note ? note dos-based software
78 m pd78076, 78078 appendix b. related documents documents related to devices document name document no. english japanese m pd78078, 78078y subseries users manual u10641e u10641j m pd78076, 78078 data sheet this document u10167j m pd78p078 data sheet u10168e u10168j 78k/0 series users manualinstructions u12326e u12326j 78k/0 series instruction table u10903j 78k/0 series instruction set u10904j m pd78078 subseries special function register table iem-5607 78k/0 series application notebasic (iii) u10182e u10182j caution the related documents listed above are subject to change without notice. be sure to use the latest version for designing, etc.
79 m pd78076, 78078 documents related to development tools (user's manuals) document name document no. english japanese ra78k series assembler package operation eeu-1399 eeu-809 language eeu-1404 eeu-815 ra78k series structured assembler preprocessor eeu-1402 u12323j ra78k0 assembler package operation u11802e u11802j language u11801e u11801j structured assembly language u11789e u11789j cc78k series c compiler operation eeu-1280 eeu-656 language eeu-1284 eeu-655 cc78k/0 c compiler operation u11517e u11517j language u11518e u11518j cc78k/0 c compiler application note programming know-how eea-1208 eea-618 cc78k series library source file u12322j pg-1500 prom programmer eeu-1335 u11940j pg-1500 controller pc-9800 series (ms-dos tm ) based eeu-1291 eeu-704 pg-1500 controller ibm pc series (pc dos tm ) based u10540e eeu-5008 ie-78k0-ns to be prepared to be prepared ie-78001-r-a to be prepared to be prepared ie-78k0-r-ex1 to be prepared to be prepared ie-78078-ns-em1 to be prepared to be prepared ie-78078-r-em u10775e u10775j ep-78064 eeu-1469 eeu-934 sm78k0 system simulator windows based reference u10181e u10181j sm78k series system simulator external part user open u10092e u10092j interface specifications id78k0-ns integrated debugger reference to be prepared u12900j id78k0 integrated debugger ews based reference u11151j id78k0 integrated debugger windows based guide u11649e u11649j id78k0 integrated debugger pc based reference u11539e u11539j caution the related documents listed above are subject to change without notice. be sure to use the latest version for designing, etc.
80 m pd78076, 78078 documents related to embedded software (user?s manuals) document name document no. japanese english 78k/0 series real-time os basics u11537e u11537j installation u11536e u11536j 78k/0 series os mx78k0 basics u12257e u12257j other documents document name document no. english japanese ic package manual c10943x semiconductor device mounting technology manual c10535e c10535j quality grades on nec semiconductor devices c11531e c11531j nec semiconductor device reliability/quality control system c10983e c10983j guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e c11892j guide to quality assurance for semiconductor devices mei-1202 microcomputer product series guide u11416j caution the related documents listed above are subject to change without notice. be sure to use the latest version for designing, etc.
81 m pd78076, 78078 [memo]
82 m pd78076, 78078 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
83 m pd78076, 78078 nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. cumbica-guarulhos-sp, brasil tel: 011-6465-6810 fax: 011-6465-6829 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j97. 8
m pd78076, 78078 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. fip and iebus are trademarks of nec corporation. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at and pc dos are trademarks of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.

▲Up To Search▲

Price & Availability of UPD78078GF-XXX-3BA

	To Download UPD78078GF-XXX-3BA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .